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S4008V1C
WCFS4008V1C
512K x 8 Static RAM
Features
* High speed -- tAA = 12 ns * 2.0V Data Retention * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE and OE features Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The WCFS4008V1C is available in standard 400-mil-wide 36-pin SOJ package and 44-pin TSOP II package with center power and ground pinout.
Functional Description
The WCFS4008V1C is a high-performance CMOS Static RAM organized as 524K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and
Logic Block Diagram
Pin Configuration
SOJ Top View
TSOP II Top View
NC A18 A17 A16 A15 OE I/O7 I/O6 GND VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC
I/O0
INPUT BUFFER
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
I/O1
ROW DECODER
I/O2
SENSE AMPS 512K x 8 ARRAY
I/O3 I/O4 I/O5
CE WE OE
COLUMN DECODER
POWER DOWN
I/O6 I/O7
A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A5 A6 A7 A8 A9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
NC NC A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC VSS I/O2 I/O3 WE A5 A6 A7 A8 A9 NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
NC NC NC A18 A17 A16 A15 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC NC NC
Selection Guide
WCFS4008V1C 12ns Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Comm'l Comm'l 12 85 10
A 11 A 12 A 13 A14 A15 A16 A17 A18
WCFS4008V1C
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................-65xC to +150xC Ambient Temperature with Power Applied............................................-55xC to +125xC Supply Voltage on VCC to Relative GND[1] .... -0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[1] ....................................-0.5V to VCC + 0.5V Range Commercial Ambient Temperature 0C to +70C VCC 3.3V 0.3V DC Input Voltage[1] ................................ -0.5V to VCC + 0.5V Current into Outputs (LOW) ........................................ 20 mA
Operating Range
Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current --TTL Inputs Automatic CE Power-Down Current --CMOS Inputs GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Comm'll Comm'l Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.0 -0.3 -1 -1 WCFS4008V1C 12ns Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 85 40 Max. Unit V V V V A A mA mA
ISB2
10
mA
Capacitance[2]
Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 8 8 Unit pF pF
Note: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns 2. Tested initially and after any design or process changes that may affect these parameters.
2
WCFS4008V1C
AC Test Loads and Waveforms
3.3V OUTPUT 5 pF INCLUDING JIG AND SCOPE (a) R2 351 R1 317 50 OUTPUT * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT Z0 =50 30pF* VTH = 1.5V
(b)
ALL INPUT PULSES 3.3V 90% GND Rise time > 1 V/ns 10% 90% 10% Fall time: > 1 V/ns
(c)
3
WCFS4008V1C
AC Switching Characteristics[3] Over the Operating Range
WCFS4008V1C 12ns Parameter READ CYCLE tpower[4] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE
[7, 8]
Description VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z
[5, 6] [6] [5, 6]
Min. 1 12
Max.
Unit ns ns
12 3 12 6 0 6 3 6 0 12 12 8 8 0 0 8 6 0 3 6
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CE LOW to Power-Up CE HIGH to Power-Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z
[6]
WE LOW to High Z[5, 6]
Notes: 3. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 4. tPOWER gives the minimum amount of time that the power supply should be at stable, typical Vcc values until the first memory access can be performed. 5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
4
WCFS4008V1C
Switching Waveforms
Read Cycle No. 1[9, 10]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled)[10, 11]
ADDRESS tRC CE
tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE
DATA OUT
Notes: 9. Device is continuously selected. OE, CE = VIL. 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE transition LOW.
5
WCFS4008V1C
Switching Waveforms (continued)
Write Cycle No. 1(WE Controlled, OE HIGH During Write)[12, 13]
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA
OE tSD DATA I/O NOTE 14 tHZOE DATAIN VALID tHD
Write Cycle No. 2 (WE Controlled, OE LOW)[13]
tWC ADDRESS tSCE CE
tAW tSA WE tSD DATA I/O NOTE 14 tHZWE DATA VALID tPWE
tHA
tHD
tLZWE
Truth Table
CE H L L L OE X L X H WE X H L H I/O0 - I/O7 High Z Data Out Data In High Z Power-Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Notes: 12. Data I/O is high-impedance if OE = VIH. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 14. During this period the I/Os are in the output state and input signals should not be applied.
6
WCFS4008V1C
Ordering Information
Speed (ns) 12 Ordering Code WCFS4008V1C-JC12 WCFS4008V1C-TC12 Package Name J T Package Type 36-Lead (400-Mil) Molded SOJ 44-pin TSOP II Operating Range Commercial
Package Diagrams
36-Lead (400-Mil) Molded SOJ J
7
WCFS4008V1C
Package Diagrams (continued)
44-Pin TSOP II T
8
WCFS4008V1C
512K x 8 Static RAM
Revision History
Document Title: WCFS4008V1C 32K x 8 3.3V Static RAM REV. ** ISSUE DATE 4/12/2002 ORIG. OF CHANGE XFL DESCRIPTION OF CHANGE New Datasheet

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